1. Field of the Invention
The present invention relates to a digital interface unit for control of a peripheral device and, more particularly, to a digital interface unit for control of a peripheral device, especially a positioning device, comprising a data input for receipt of a control value or values for the peripheral device, an output register or registers for storing the control value or values received via the data input and for preparation of the control value or values for output to the peripheral device, wherein the output register or registers has a first control input and means for outputting the control value or values in response to a signal at the first control input.
2. Prior Art
In microprocessor systems digital interface units are used for control of peripheral devices, which adapt the internal data bus of the microprocessor system to the external data bus between the microprocessor system and the peripheral device. An output circuit for a microprocessor system, for example, is known from Philippow, xe2x80x9cTaschenbuch der Elektrotechnikxe2x80x9d (Pocketbook of Electrical Engineering), 3rd Ed., Vol. 3, p. 1126. This output circuit has an output register, which receives a data word to be output via the internal data bus of the microprocessor system, prepares it and places it on the external data bus for the peripheral device. The control of the data output occurs by means of a control signal designated a data strobe signal, which controls the output register for importing the data word on the internal data bus, so that all data bits of the new data word appear at exactly the same time on the external data bus, which is important especially for controlling a positioning device, since otherwise the positioning device receives an incorrect control value for a short time.
It is however disadvantageous that the interface unit blocks the internal data bus of the microprocessor system during output of a new data word, since the new data word must be present on the internal data bus at exactly this time. Hardly any time exists for this. It is also not possible, for example, to already transfer the new data word to the interface unit prior to the provided time point and to employ the internal data bus subsequently for other purposes. Accordingly the usefulness of the internal data bus of the microprocessor system is limited.
In an interface unit with several output registers it is thus not possible to transmit a complete set of several new control values simultaneously to all output registers, since the individual output registers must be loaded sequentially over the internal data bus and the respective new control values immediately imported.
It is an object of the present invention to provide an interface unit for controlling a peripheral device which limits the usefulness of the internal data bus of the microprocessor system as little as possible and despite the output of a new data word guarantees that all data bits are output simultaneously so that incorrect control of the peripheral device is prevented. Especially the simultaneous output of a complete set of new control values should be possible with an interface unit according to the invention provided with several output registers.
This object, and others which will be made more apparent hereinafter, are attained in a digital interface unit for control of a peripheral device, especially a positioning device, comprising a data input for receipt of a control value for the peripheral device, an output register for storing the control value received at the data input and for preparation of the control value for output to the peripheral device, wherein the output register has a first control input and means for outputting the control value input to it on activation of or in response to a signal at the first control input.
According to the invention a buffer register is connected between the data input and the output register for intermediate storage of the control value applied to the control input of the output register.
The buffer register provides the advantage that a new data word can be received from the internal bus independently of the output of a data word from the unit, i.e. at any time.
The term xe2x80x9cperipheral devicexe2x80x9d here means any electrically controllable component, device or adjusting member. The interface unit according to the invention is preferably used for control of magnetic valves in injection units.
In a preferred embodiment of the invention the interface unit has several parallel output registers, which control respective peripheral devices or contain respective control values for the same peripheral devices. During the control of the magnetic valve the individual output registers, for example can receive the electric current passing through the magnetic valve and control parameters for regulation of the magnetic valve. Each output register is connected to a respective buffer register. The input side of the buffer registers are connected with the address bus of the microprocessor system to allow selective addressing.
In another advantageous aspect of the invention transmission of individual data words from the microprocessor system to the interface unit does not occur individually at the predetermined time point, but a sequence of several data words is transmitted one after the other to the interface unit and intermediately stored there in a data memory. The internal data bus of the microprocessor system is rarely blocked, which is especially notable for control magnetic valves, since the sequence of control values is not varied during the closing process of the magnetic valve, so that the control values of a closing sequence can be transmitted without loss of function to the interface unit. After transmission of a sequence of control values to the interface unit, the individual controls values are then sequentially read out from the data memory and written into the output register.
The control of the sequential output of the intermediately stored control values to the output register occurs preferably via a control signal which is generated by the microprocessor system. The microprocessor system in this case of course has no further influence on the sequence and the control values of the intermediately stored sequence itself during the individual output, however the microprocessor system can still control the time of output. The control signal can be fed to the interface unit by a binary control line, whereby data and address buses of the microprocessor system advantageously remain free.
According to another aspect of the invention the interface unit has two operating modes. One of the operating modes allows a direct write of a new data word into the input side of the buffer memory, while a complete sequence of data words is transferred in another operating mode. In that mode a multiplexer is connected to a respective output register, which either directly connects the output register with a buffer memory or allows the storage of a complete sequence with intermediate switching of the data memory.